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Resolve All XAU5 XTSFI Shorts Stop Outs on Alpari ...

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saherelm
2024-02-04 12:27:27 +03:30
parent 949969626c
commit a10aa4bb97
3 changed files with 102 additions and 0 deletions
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BKP/Main/Providers/x-saherelm.xau5.provider.indicators.lib.mq5
+34
View File
@@ -6888,6 +6888,15 @@ bool XAU5XTSFIHasShortSignal()
// //
|| ||
// //
(mConditions.isXTMBullish &&
mConditions.isXAMABullish &&
mConditions.isXTDBullOverBear &&
mConditions.isXCHMASCTrendsUp &&
mConditions.isXTSCurrentOverMediest &&
mConditions.isXTDSignalCrossedOverBear)
//
||
//
((mConditions.isXTDBullOverBear && ((mConditions.isXTDBullOverBear &&
mConditions.isXTDSignalOverBear && mConditions.isXTDSignalOverBear &&
mConditions.isXTSCurrentOverMediest) && mConditions.isXTSCurrentOverMediest) &&
@@ -6991,6 +7000,31 @@ bool XAU5XTSFIHasShortSignal()
((mConditions.isXCHMALCFastOverSlow || ((mConditions.isXCHMALCFastOverSlow ||
mConditions.isXCHMALCFastCrossedOverSlow) && mConditions.isXCHMALCFastCrossedOverSlow) &&
( (
//
mConditions.isXRSICrossedUnderShortExit
//
||
//
((mConditions.isXTDSignalVale &&
mConditions.isXTDBullishVale &&
mConditions.isXCHLHSCMCLLSame &&
mConditions.isXCHMASCUnderMin &&
mConditions.isXTSCurrentOverMediest) &&
(
//
(mConditions.isXTDBullUnderBear &&
mConditions.isXTDSignalUnderBear)
//
||
//
(mConditions.isXCHMASCCrossedUnderMin &&
mConditions.isXTSCurrentCrossedOverMediest)
//
)
//
)
//
||
// //
(mConditions.isXTMNeutural && (mConditions.isXTMNeutural &&
mConditions.isXAMANeutural && mConditions.isXAMANeutural &&
Projects/XAU5/Providers/x-saherelm.xau5.provider.indicators.lib.mq5
+34
View File
@@ -6888,6 +6888,15 @@ bool XAU5XTSFIHasShortSignal()
// //
|| ||
// //
(mConditions.isXTMBullish &&
mConditions.isXAMABullish &&
mConditions.isXTDBullOverBear &&
mConditions.isXCHMASCTrendsUp &&
mConditions.isXTSCurrentOverMediest &&
mConditions.isXTDSignalCrossedOverBear)
//
||
//
((mConditions.isXTDBullOverBear && ((mConditions.isXTDBullOverBear &&
mConditions.isXTDSignalOverBear && mConditions.isXTDSignalOverBear &&
mConditions.isXTSCurrentOverMediest) && mConditions.isXTSCurrentOverMediest) &&
@@ -6991,6 +7000,31 @@ bool XAU5XTSFIHasShortSignal()
((mConditions.isXCHMALCFastOverSlow || ((mConditions.isXCHMALCFastOverSlow ||
mConditions.isXCHMALCFastCrossedOverSlow) && mConditions.isXCHMALCFastCrossedOverSlow) &&
( (
//
mConditions.isXRSICrossedUnderShortExit
//
||
//
((mConditions.isXTDSignalVale &&
mConditions.isXTDBullishVale &&
mConditions.isXCHLHSCMCLLSame &&
mConditions.isXCHMASCUnderMin &&
mConditions.isXTSCurrentOverMediest) &&
(
//
(mConditions.isXTDBullUnderBear &&
mConditions.isXTDSignalUnderBear)
//
||
//
(mConditions.isXCHMASCCrossedUnderMin &&
mConditions.isXTSCurrentCrossedOverMediest)
//
)
//
)
//
||
// //
(mConditions.isXTMNeutural && (mConditions.isXTMNeutural &&
mConditions.isXAMANeutural && mConditions.isXAMANeutural &&
Providers/x-saherelm.xau5.provider.indicators.lib.mq5
+34
View File
@@ -6888,6 +6888,15 @@ bool XAU5XTSFIHasShortSignal()
// //
|| ||
// //
(mConditions.isXTMBullish &&
mConditions.isXAMABullish &&
mConditions.isXTDBullOverBear &&
mConditions.isXCHMASCTrendsUp &&
mConditions.isXTSCurrentOverMediest &&
mConditions.isXTDSignalCrossedOverBear)
//
||
//
((mConditions.isXTDBullOverBear && ((mConditions.isXTDBullOverBear &&
mConditions.isXTDSignalOverBear && mConditions.isXTDSignalOverBear &&
mConditions.isXTSCurrentOverMediest) && mConditions.isXTSCurrentOverMediest) &&
@@ -6991,6 +7000,31 @@ bool XAU5XTSFIHasShortSignal()
((mConditions.isXCHMALCFastOverSlow || ((mConditions.isXCHMALCFastOverSlow ||
mConditions.isXCHMALCFastCrossedOverSlow) && mConditions.isXCHMALCFastCrossedOverSlow) &&
( (
//
mConditions.isXRSICrossedUnderShortExit
//
||
//
((mConditions.isXTDSignalVale &&
mConditions.isXTDBullishVale &&
mConditions.isXCHLHSCMCLLSame &&
mConditions.isXCHMASCUnderMin &&
mConditions.isXTSCurrentOverMediest) &&
(
//
(mConditions.isXTDBullUnderBear &&
mConditions.isXTDSignalUnderBear)
//
||
//
(mConditions.isXCHMASCCrossedUnderMin &&
mConditions.isXTSCurrentCrossedOverMediest)
//
)
//
)
//
||
// //
(mConditions.isXTMNeutural && (mConditions.isXTMNeutural &&
mConditions.isXAMANeutural && mConditions.isXAMANeutural &&